1. Field of the Invention
The present invention relates to flip-chip semiconductor devices, particularly to power/ground pad arrangement of flip-chip semiconductor devices.
2. Description of the Related Art
With the improvement of the fine processing technology, semiconductor devices which have been conventionally integrated within plural separate chips can be integrated within a single semiconductor chip.
This is, however, accompanied by the increase in a total number of signal terminals of the single semiconductor chip. The increase in the number of signal pads may cause a problem, because conventional quad flat packaging (QFP) and pin grid array packaging (PGA) may not provide a required number of signal terminals. Accordingly, the flip-chip packaging technique has been increasingly used, instead of the QFP and PGA techniques.
Flip chip packages have various advantages. Firstly, total numbers of signal terminals can be increased. Additionally, power pads can be arranged at arbitrary places of internal areas of semiconductor chips, by using a build-up board within which a power supply plane is integrated. This effectively improves power supply capability within the semiconductor chip.
The flip-chip packaging allows VDD/GND pads to be arranged over the internal area within which internal circuits are integrated as disclosed in Japanese Laid Open Patent Applications Nos. Jp-2003 68852A, and Jp-2003 124318A. In such a flip-chip semiconductor device, the peripheral portion of the internal area experiences potential drop of power supply lines, most severely.
FIG. 1 illustrates an exemplary arrangement of pads and power supply circuitry within a conventional flip-chip. It should be noted that FIG. 1 partially illustrates the structure of the conventional flip-chip semiconductor device; FIG. 1 only illustrates a one-fourth portion at the lower left of the entire flip-chip semiconductor device. The lower right, upper left and upper right portions of the semiconductor device are correspondingly configured in the right-to-left symmetry and in the top-to-bottom symmetry. These portions are not shown in FIG. 1.
The flip-chip semiconductor device is provided with power pads 3 arranged in rows and columns over an internal area within which logic circuits are integrated. It should be noted that the term “power pad” collectively denotes both of the VDD pad fed with a power supply level, and the GND pad fed with an earth ground level. In FIG. 1, the power pads 3 fed with the power supply level are denoted by symbols “V”, and the power pads 3 fed with the earth ground level are denoted by symbols “G”. The internal area is surrounded by an I/O buffer region 6 within which I/O buffers are integrated. The symbols “S” within the I/O buffer region 6 denotes signal I/O pads connected with the I/O buffers.
The electric power is distributed through first-level interconnections 1 arranged in the uppermost interconnection level, and second-level interconnections 2 arranged in the second uppermost interconnection level. The first-level interconnections 1 are connected with the pads 3 through branch interconnections. The first-level interconnections 1 are connected with the second-level interconnections 2 through via contacts 4. The first-level interconnections 1 and the second-level interconnections 2 are arranged orthogonally to each other; the first-level interconnections 1 are extended in the horizontal direction, for example, and the second-level interconnections 2 are extended in the vertical direction. Chip peripheral power supply loops 5 are arranged at the peripheral portion of the internal area. Horizontally-extending portions of the chip peripheral power supply loops 5 are disposed at the uppermost interconnection level, and vertically-extending portions of the chip peripheral power supply loops 5 are disposed at the second uppermost interconnection level.
For example, electric power is delivered from a VDD pad denoted by a symbol “P1” to a position “c” at the left end of the internal area, through a first-level interconnection 1 between the pad “P1” and a via contact 4 disposed at a position “b”, and a chip peripheral power supply loops 5 between the positions “b” and “c”. The chip peripheral power supply loop 5 is integrated at the second uppermost interconnection level between the positions “b” and “c”.
Correspondingly, electric power is delivered from a VDD pad denoted by a symbol “P2” to a position “g” at the lower end of the internal area, through a first-level interconnection 1 between the pad “P2” and a via contact 4 disposed at a position “e”, a second-level interconnection 2 between the via contacts 4 disposed at the positions “e” and “f”, and a chip peripheral power supply loop 5 between the positions “f” and “g”.
In the conventional flip-chip semiconductor device shown in FIG. 1, the first-level interconnections 1 are extended in the horizontal direction except for the branch interconnections connected with the pads 3, and the second-level interconnections 2 are extended in the vertical direction. Such structure undesirably suffers from increased difference in the interconnection resistance caused by the difference in the interconnection structure difference depending on the positions over the semiconductor chip. For example, the interconnection resistance between the pad “P2” near the lower end of the chip and the position “g” is largely different from that between the pad “P1” near the left end of the chip and the position “c”.
A specific calculation result of the interconnection resistances is described in the following, depicting the difference in the interconnection resistances. The calculation is performed under the conditions as follows:                width of the first-level interconnections 1: 1.6 μm,        sheet resistance thereof: 0.0175 Ω/□,        width of the second-level interconnection 2: 1.6 μm,        sheet resistance thereof: 0.0175 Ω/□,        size of the pads 3: 120×120 μm2         pitch of the pads 3 (center-to-center): 250 μm,        width of the chip peripheral power supply loops 5: 10 μm,        resistance of the via contacts 4: 0.06 Ω/piece,        distance between the center point of pad P1 and the position “a”: 70 μm,        distance between the center point of the pad P2 and the position “d”: 70 μm,        distance between the positions “a” and “b”: 180 μm,        distance between the positions “d” and “e”: 125 μm,        distance between the positions “b” and “c”: 320 μm,        distance between the positions “e” and “f”: 250 μm, and        distance between the positions “f” and “g”: 125 μm        
It should be noted that a certain first-level interconnection 1 is assumed to be connected with a certain second-level interconnection 2 through a single via contact 4 within the internal area in this calculation, while the first-level and second level interconnections 1 and 2 are assumed to be connected with the chip peripheral power supply loops 5 through six via contacts 4.
When interconnection resistances are given under the above-explained conditions as follows:
(1) Resistance Value Between Pad P1 and Position “b”0.0175 Ω/□×(70/120)+0.0175 Ω/□×(180/1.6)+0.06/6=1.989Ω;(2) Resistance Value Between Pad P1 and Position “c”Resistance value (1)+0.0175 Ω/□×(320/10)=2.549Ω(3) Resistance Value Between Pad P2 and Position “f”0.0175 Ω/□×(70/120)+0.0175 Ω/□×(125/1.6)+0.06+0.0175 Ω/□×(250/1.6)=4.172Ω; and(4) Resistance Value Between Pad P2 and Position “g”Resistance value (3)+0.06/6+0.0175 Ω/□×(125/10)=4.401Ω.
As a consequence, a resistance difference “ΔR” from the associated pads (the pads P1 and P2) of the positions “c” and “g” is given as follows:ΔR=4.401Ω−2.549Ω=1.852Ω.This implies that the resistance between the pad P2 the position “g” is increased by +73% with respect to the resistance between the pad P1 and the position “c”.
As thus described, the power interconnection resistances between the pads 3 and the positions near the right/left edges of the internal area are relatively lower than those between the pads 3 and the positions near the top/bottom edges of the internal area. This may cause a problem that potential drops along the power supply interconnections are largely different between portions near the top/bottom edges and portions near the right/left edges. More specifically, a potential drop of a power supply voltage must be suppressed to approximately 10 mV in a high-end semiconductor device, in order to reduce the delay of flipflops integrated within the device down to 10 ps or less, which is 10% of required setup time of the flipflops (approximately 100 ps). For example, in such a case that an average consumed current of a high-driven buffer is assumed to be nearly 3.08 mA for each clock cycle, and the high-driven buffer is arranged at the above-described point “g”, the high-driven buffer experiences a power supply potential drop of 13.56 mV (3.08 mA×4.401Ω), which largely exceeds 10 mV. This is undesirable for satisfying operation requirements of the semiconductor device.
As previously explained, conventional flip-chip semiconductor devises requires a special circuit arrangement for dealing with delay difference caused by different potential drops between upper/lower edge portions and right/left edge portions, especially when high-drive buffers are arranged in the upper/lower edge portions and the right/left edge portions.
Japanese Laid-Open Patent Application No. Jp-2000 277656A discloses a multi-level printed circuit board having interconnections arranged in a symmetrical manner; however, this document does not disclose pad and interconnection arrangement of a flip-chip semiconductor device.
Additionally, Japanese Laid-Open Patent Application No. Jp-2002 190526A discloses a flip-chip semiconductor device in which I/O cells are arranged in the peripheral portion of the device. In this flip-chip semiconductor device, power pads used for supplying electrical power to the I/O cells are positioned medial to the region in which signal pads of the I/O cells.